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Espressif Systems /ESP32-S3 /SPI2 /CLK_GATE

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Interpret as CLK_GATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_EN)CLK_EN 0 (MST_CLK_ACTIVE)MST_CLK_ACTIVE 0 (MST_CLK_SEL)MST_CLK_SEL

Description

SPI module clock and register clock control

Fields

CLK_EN

Set this bit to enable clk gate
MST_CLK_ACTIVE

Set this bit to power on the SPI module clock.
MST_CLK_SEL

This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data